The present invention relates to high-speed data interfaces, and more particularly to reducing skew between inputs provided at high-speed data interfaces.
The demand for higher speed data interfaces has increased dramatically the past few years, and this increase shows no signs of abating. As an example, huge amounts of data must be transferred from memory devices to other integrated circuits for such applications as music and video playback, image processing, graphics, and others. Many of these demanding applications run on advanced field programmable gate arrays (FPGAs) such as those developed by Altera Corporation of San Jose, Calif.
New interface techniques, such as Double data rate (DDR) and others, have been developed to support these data rates. In a DDR interface, data is read on each (rising and falling) edge of a strobe or clock signal. For example, a typical DDR memory interface can include a data strobe signal (DQS) transmitted in parallel with a group of data signals (DQ) to a receiver. The receiver uses the characteristics of the DQS signal to synchronize itself with the DQ signals. As the receiver (not the memory) typically handles this synchronization, the DQS may be edge-aligned with DQ data signals during read operations and center-aligned with DQ data signals during write operations.
As DDR interfaces increase in speed, the timing margins for communications become smaller and more susceptible to errors. Skew is the difference in arrival time between corresponding portions of the DQS signal and one or more DQ data signals transmitted at the same time. This skew can be caused by differences in signal path lengths between DQS and DQ signal lines, as well as other factors that can vary with operating voltage, temperature, and manufacturing process variations. Thus, the size of the valid sampling time window in which an interface can capture and latch data signals is reduced.
Previous methods of reducing skew include using programmable delay chains with the DQ and DQS signals to selectively delay one or more signals to compensate for skew. This method typically measures the skew at the time of design or manufacturing, which can be costly. These delays are then permanently programmed into the programmable delay chains. However, as these delay values may be fixed at an early stage of manufacturing, this technique does not compensate for certain manufacturing variations (such as process and voltage) and actual operating conditions (such as temperature, humidity, pressure) during operation.
Another prior technique uses a skew locked loop to continuously monitor the skew between DQ and DQS signal paths and adjust delay chain settings accordingly to compensate for the skew between these paths. Although skew locked loops can continuously update delay values to compensate for voltage and temperature variations in skew, they typically require the addition of a dedicated mimic signal path to measure the skew. The addition of a dedicated mimic signal path greatly increases the cost of devices, due to the addition of pins for the mimic path, as well as the cost of systems, due to the increased complexity of circuit boards. Moreover, a single skew locked loop can only track the skew between one DQ data signal path and the DQS signal path. Thus, a skew locked loop cannot determine independent delay values for each DQ data signal to individually compensate each DQ data signal for its own skew with respect to the DQS signal path.
It is therefore desirable to reduce skew from multiple sources and among all DQ and DQS signals at a minimal cost.